LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux2 is
port(

	--clk: in std_logic;
	sel : in std_logic_vector(1 downto 0);
	input1: out std_logic_vector(31 downto 0);
	input2: out std_logic_vector(31 downto 0);	
	fre_output1: in std_logic_vector(31 downto 0);
	fre_output2: in std_logic_vector(31 downto 0);	
	dta_output1: in std_logic_vector(31 downto 0);
	dta_output2: in std_logic_vector(31 downto 0);	
	tim_output1: in std_logic_vector(31 downto 0);
	tim_output2: in std_logic_vector(31 downto 0);
	shiji_fre: in std_logic;
	shiji_dta: in std_logic;
	shiji_tmt: in std_logic;
	shiji_o: out std_logic

);
end mux2;

architecture bahave of mux2 is


begin

process(sel)
begin
	

		if sel = "00" then
			input1 <= fre_output1;
			input2 <= fre_output2;	
			shiji_o <= shiji_fre;
		elsif sel = "01" then
			input1 <= dta_output1;
			input2 <= dta_output2;
			shiji_o <= shiji_dta;	
		elsif sel = "10" then
			input1 <= tim_output1;
			input2 <= tim_output2;	
			shiji_o <= shiji_tmt;
		else null;
		end if;


	
end process;



end architecture;